An electronic element package described in, for example, Japanese Patent Laid-Open No. 2006-170856 shown in FIG. 19 has a package having a recessed portion 12 and an acceleration chip 1 accommodated in the package. The acceleration chip 1 has a support portion 3 located in the center of the chip 1 and fixed to a circuit board 2 and flange portions 4 located around the support portion 3. The flange portions 4 are combined with and suspended from one end of a detecting beam 5 the other end of which is connected to the top of the support portion 3. The support portion 3, the flange portions 4, and the detecting beam 5 are integrally formed on a semiconductor substrate by a micromachine technology.
Detecting elements 6 are formed at the top of the detecting beam 5 to vary an output signal in response to distortion resulting from acceleration applied to the flange portions 4. The substrate 2 is fixed to an inner bottom surface of the package with an adhesive 7.
A bonding pad 8 and the detecting elements 6 formed on an upper end surface of the support portion 3 are electrically connected together by leads (not shown). The bonding pad 8 is connected, via gold wires 10, to external extraction terminals 9 formed on the package. The external extraction terminals 9 are connected to electrode terminals 11 formed on a bottom surface of the package using conductive films formed along walls of the package. Reference numeral 13 denotes a cap.
Japanese Patent Laid-Open No. 6-318625 describes a package in which bulkhead portions 53 are formed on one surface of an element substrate 52 on which an electronic element 51 is formed so that the bulkhead portions 53 surround the electronic element 51, with a cover substrate 55 having penetration electrodes 54 to close the opening between the bulkhead portions 53 to seal the electronic element 51, as shown in FIG. 20. Reference numeral 56 denotes an electrode formed outside the cover substrate 55 and electrically connected to the penetration electrode 54 to extract an electrode of the electronic element 51.
FIGS. 21 and 22 show an electronic element package described in Japanese Patent Laid-Open No. 2000-186931. FIG. 21 is an exploded view showing a lower glass substrate 81 and an upper glass substrate 82 of the electronic element package which have not been laminated yet. FIG. 22 is a sectional view of the laminated lower glass substrate 81 and upper glass substrate 82; the sectional view is taken along line X-X in FIG. 21.
An angular speed detecting portion 83 formed on the lower glass substrate 81 is supported by the lower glass substrate 81 at opposite ends 83a and 83b thereof. An intermediate portion 83c of the angular speed detecting portion 83 is not in contact with the lower glass substrate 81 and is thus movable. The upper glass substrate 82 is joined to a frame portion 84 provided on an outer periphery of the lower glass substrate 81 for hermetic sealing. In addition to the frame portion 84, signal output portions 85a, 85b, and 85c are formed on the lower glass substrate 81 in the external extraction electrode. The signal output portions 85a, 85b, and 85c are laminated to the upper glass substrate 82 and extracted through via holes 86.
With the configuration in Japanese Patent Laid-Open No. 2006-170856, even when the support portion 3, the flange portions 4, and the detecting beam 5 are integrally formed on the semiconductor substrate by the micromachine technology, it is difficult to achieve a reduction in thickness. In contrast, the configurations in Japanese Patent Laid-Open Nos. 6-318625 and 2000-186931 enable a reduction in thickness, but the reliability of the hermetic seal structures in these configurations is still requested to be improved.
Furthermore, the configuration in Japanese Patent Laid-Open No. 6-318625 needs to prepare the cover substrate 55 with the penetration electrodes 54 preformed therein and to laminate the cover substrate 55 to the element substrate 52. Japanese Patent Laid-Open No. 2000-186931 also needs to preform the via holes 86.
An object of the present invention is to provide an electronic element package which enables a reduction in thickness and which eliminates the need to form penetration electrodes or via holes as external extraction electrodes.